Principal CPU Microarchitect

*** Work Permits For The UK can be sponsored for this role ***

Our client is one of the world's leading technology companies with over 200 000 employees and operating in 170 countries around the world.

Their spirit of innovation has led our client to work in close partnership with leading academic institutions in the UK to develop and refine the latest technologies, having invested in dedicated R&D facilities and teams in Cambridge, London, Edinburgh, and Ipswich (which are part of a global R&D team of almost 100 000 people).

We are looking for a Principal CPU Microarchitect to be ideally be based in the Cambridge office and will offer a world-class remuneration package and our client can offer relocation assistance and visa sponsorship.

Principal Micro-Architect Job Summary

We are seeking a Principal CPU Microarchitect to join the Kirin CPU Team at our client's R&D facility in Cambridge, UK, working on next-generation out-of-order processor cores powering our client's flagship mobile and compute platforms. You will define and evaluate microarchitectural features across the front-end, execution engine, and memory subsystem through cycle-accurate modelling and rigorous workload analysis, with a focus on workload-driven innovation for demanding mobile workloads. This is a pure microarchitecture and architecture modelling role, working closely with compiler, runtime, and downstream design teams.

Key Responsibilities:

• Define and specify microarchitectural features across pipeline stages — fetch/decode, OoO execution, LSU, prefetchers, branch prediction, and cache hierarchy
• Build and maintain cycle-accurate performance models (gem5 or equivalent) to evaluate new features against SPEC CPU 2017 and representative mobile workloads
• Drive workload analysis combining cycle-accurate gem5 modelling with simpleperf, hardware counters, and trace-based methods to identify bottlenecks and quantify uplift opportunities
• Co-design ISA extensions with compiler and runtime teams, including ISA extensions, prefetch hints, and semantic acceleration primitives
• Author detailed microarchitecture specifications and partner with design teams on implementation trade-offs
• Mentor junior engineers and contribute to the team's technical direction across multiple parallel tracks (prefetch, semantic acceleration, AI4CPU)

Required:

• MSc or PhD in Computer Science, Electrical Engineering, or equivalent industry experience
• Hands-on CPU microarchitecture experience on out-of-order cores
• Deep working knowledge of at least one major area: branch prediction, prefetching, OoO execution, memory subsystem, or cache coherence
• Proven experience with cycle-accurate simulators (gem5 or proprietary equivalents)
• Strong workload analysis skills — performance counter methodology, top-down analysis, trace inspection
• Proficient in C++ and Python for modelling, analysis tooling, and automation
• Familiarity with ARMv8/v9, Intel x86_64 or RISC-V ISA at the microarchitectural level

Desired:

• PhD in computer architecture with publications at ISCA, MICRO, HPCA, or ASPLOS
• Experience with dynamic language runtimes (V8, SpiderMonkey, ArkCompiler) and JIT/AOT code generation
• Exposure to AI/ML inference workloads on CPU and CPU-NPU co-design
• Track record of features that shipped in production silicon
• Familiarity with LLM-driven design exploration or agentic optimisation flows

Please ignore the salary ranges included on the job board - this is a senior-level position within a world-class company and will pay accordingly