Senior DFT Engineer - LPU

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join NVIDIA and lead the charge in revolutionizing AI technology! As a Senior DFT Engineer, you'll develop and implement powerful Design for Test (DFT) architecture for next-gen AI Chips. Collaborate with cross-functional teams to apply innovative DFT methodologies, ensuring high-quality products that compete on a global scale. This is your opportunity to work on innovative technology in an encouraging and diverse environment! What you'll be doing: Define and implement SCAN, MBIST, and JTAG debug structures, applying sophisticated DFT techniques to drive post-Si testing plans. Drive the creation of ATPG and MBIST test vectors. Build DFT timing constraints and partner with the Physical Design and STA sign-off team to ensure timing closure in DFT mode. Work closely with the post-silicon team to bring up test patterns on silicon, ensuring flawless bringup. Collaborate with the CAD methodology team to introduce innovative and intelligent AI driven optimizations, improving efficiency in DFT implementation. What we need to see: Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) with 5+ years of industry experience in DFT for high-performance ASICs. Practical experience with SCAN/MBIST/Test generation tools and processes for large SoC/ASIC. Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, scan compression, MBIST, IEEE 1500 standard, and LBIST. Familiarity with ATPG Streaming SCAN Network (SSN) implementation. Experience with UDFMs like Cell Aware and Small Delay Defect. Consistent track record in yield estimation and test optimization. Experience working with real silicon in the lab and debugging DFT test sequences on ATE to resolve silicon issues. Solid understanding of RTL to GDS methodologies and formal equivalence. Excellent coding skills in Tcl and Python. Outstanding interpersonal and organizational skills with a strong desire to work as part of a team with varied strengths. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until June 16, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.