Senior ASIC Verification Engineer

Senior ASIC Verification Engineer — Janus AI Safety Chip

Location: Stockholm, Berlin, or remote in EU/UK time zone (Cape Town ±2 hours)

Reports to: Head of Verification

Start: Within 60 days

Equity: 0.5%–1.5% with 4-year vest, 1-year cliff

Cash: €130K–€170K base depending on location and seniority

The opportunity in one sentence

Vantage Technologies has filed the first patent in the world for a hardware AI verification chip — a silicon device that checks every AI decision in 62 nanoseconds and physically blocks unsafe ones through a gate no software can override. We are taping out on a EUROPRACTICE 28nm shuttle in 2027 with TSMC 5nm production silicon following. You will be employee #4 or #5, building the verification environment that proves this design is correct before silicon goes to the fab.

What you'll do

Extend our existing UVM testbench (currently passing 10M+ vectors at 62.4ns confirmed latency) to 50M+ vectors with full functional, code, and assertion coverage. Lead formal verification using JasperGold or VC Formal on the safety-critical block gate logic. Drive sign-off readiness for the EUROPRACTICE 28nm shuttle. Architect the regression infrastructure so it runs unattended overnight and surfaces only signal. Work directly with CEO and verification lead.

What you bring

8+ years of ASIC verification experience with at least two tape-outs you can describe in detail. Deep SystemVerilog/UVM. Comfortable with formal verification — JasperGold, VC Formal, or equivalent. Experience verifying safety-critical or security-critical IP (any of: ARM SafetyIsland, automotive ASIL-D, payment processors, cryptographic engines).

What we don't want

Founders who have only done verification at a single FAANG. Engineers who need someone else to write the test plan. Anyone who thinks NDA-bound IP is something to discuss on Twitter.

The honest pitch

You will work with people whose names will be on patents in your field for decades. The patent is filed. The code compiles. The regulatory demand is real and dated. The equity is significant for the third or fourth verification hire in a company that has a credible $1T enterprise value trajectory in 10 years. The risk is silicon — every chip company can fail to tape out on schedule, including ours. We will not pretend otherwise.

Apply with: a CV, a list of tape-outs you can speak to, and one paragraph on a verification bug you found that no one else would have caught.