#22757-Physical Design Engineer

Date: 8 Jun 2026 Company: Qualitest Group Country/Region: IN New vendor Opening req for onboarding process 3 google Level 2 engineersPhysical Design engineerJob Title: Senior Physical Design EngineerLocation: Bangalore / Hybrid modeType: Full TimeIndustry: Semiconductors / VLSI / ASIC DesignJob Summary:We are seeking a skilled Senior Physical Design Engineer to join our chip development team. In this role, you will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII. You’ll collaborate closely with RTL design, verification, and DFT teams to ensure successful tape-out of high-performance, low-power silicon designs. Key Responsibilities: Own and execute physical design tasks including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC). Work on timing closure using STA tools and fix violations across multiple PVT corners. Perform IR drop and EM analysis, drive fixes to meet power integrity requirements. Collaborate with cross-functional teams including RTL, DFT, packaging, and manufacturing. Debug issues across PnR, DRC/LVS, and timing flows, and provide root-cause analysis and solutions. Contribute to flow development and automation to improve quality and efficiency. Work on block level/sub-system level in latest Backend low power complex chip designs. Required Qualifications: B.E in Electronics/ M.Tech in VLSI Engineering. 5+ to 8 years of experience in ASIC physical design with a proven tape-out record. Strong hands-on experience with industry-standard tools (e.g., Innovus, ICC2, PrimeTime, Voltus, Calibre). Solid understanding of timing, signal integrity, IR drop, and physical verification. Good scripting skills (TCL, Python, or Perl) for flow automation and debug. Excellent problem-solving and communication skills. Preferred Qualifications: Experience with hierarchical design methodologies. Exposure to low-power design techniques (UPF) low power. Familiarity with advanced nodes (5nm or below) 2nm/3nm project exposure would be a plus.